1. Field of the Invention
The present invention relates to a semiconductor memory device, and more particularly, to an operation control circuit for a semiconductor memory device including a single data rate (SDR) mode and a double data rate (DDR) mode.
2. Description of the Related Art
In general, a computer system includes a central processing unit (CPU) for executing instructions and a main memory for storing the data and the program code required for CPU operation. Increasing the CPU operating speed improves the performance of the computer system. One way to increase the CPU operating speed is by eliminating the CPU waiting time thereby shortening the time required for accessing the main memory. Accordingly, a need remains for a Synchronous Dynamic Random Access Memory (SDRAM) operated under control of a system clock and having a short main memory accessing time.
In SDRAM devices control operations are typically responsive to pulse signals generated by the transition of a system clock. The method for generating a pulse signal responsive to the transition of the system clock can be divided into two modes: the SDR mode and the DDR mode. In the SDR mode, the pulse signal necessary to operate the SDRAM device is generated only during one directional transitions of the system clock, i.e., between a logic high to low transitions or a logic low to high transitions. In the DDR mode, the pulse signal necessary to operate the SDRAM device is generated during both directional transitions of the system clock, i.e., a logic high to low transitions and a logic low to high transitions.
Since data is input into or output from an SDRAM device on a rising or falling edge of a clock signal, the DDR mode is operable in a wide operational frequency range (bandwidth). Therefore, the DDR mode has the advantage of operating at very high speeds. However, the SDR mode has the advantage of a simple design. Typically, the DDR mode is used in memory devices for high speed systems and the SDR mode is used in all other memory devices.
FIG. 1 is a block diagram showing the operation controller of a conventional semiconductor memory device employing the SDR mode. FIG. 2 is a block diagram showing the operation controller of a conventional semiconductor memory device employing the DDR mode.
In memory devices using the DDR mode, signal set-up and hold times are defined for outputting data. These set-up and hold time are different for memory devices using the SDR mode. Accordingly, memory devices using the DDR mode and memory devices using the SDR mode are not interchangeable. Additionally, conventional semiconductor memory devices including operation control circuits which employ either SDR or DDR modes have no way of switching from one mode to another. Thus, production efficiency deteriorates and costs increase.